1. Field of the Invention
The present invention relates to methods and apparatus for implementing a power down in a memory device and, more particularly to techniques that avoid potential complications resulting from implementing a power down that occurs during a read burst on a dynamic random access memory.
2. Description of the Related Art
In electronic memory devices, such as dynamic random access memories (DRAMs), it is often desirable to conserve power. For example, conventional DRAM chips are capable of entering a power down state when commanded by an external signal. To save additional power, some DRAM chips also suspend clock signals during a power down, which is particularly advantageous in devices that operate on battery power, such as mobile devices. Normally, a memory device such as a DRAM is commanded to enter a power down state while the memory device is not actively reading or writing data, since implementing a power down during a read or write operation can result in malfunction of the memory device.
One such memory device is a double data rate synchronous dynamic random access memory (DDR SDRAM), which is capable of reading out stored data in read bursts. With each read command, a read burst operation sequentially transmits a given number of data words from the memory device to the system in which the memory device is operating. A DDR SDRAM chip facilitates data transfers on both edges of each successive clock cycle (i.e., both the rising and falling edges), thereby doubling the memory chip data throughput. The data, conventionally denoted as “DQ,” is driven off the chip via off-chip drivers (OCD) aligned to the rising and falling edges of data strobe signals (DQS), which are also driven off the chip. The length of a read burst is programmable such that, for example, during a read burst of length four, there are four data words driven off the chip during two clocking cycles (i.e., two data words are respectively driven off during the two high phases and two during the two low phases). The signal edges of the DQS signal are used by other devices receiving the data DQ over a set of lines (e.g., a data bus) to latch the DQ data words. Each data word consists of a set of parallel bits simultaneously driven off the chip onto respective lines by a set of respective parallel OCDs in accordance with the configuration of the DDR SDRAM (e.g., sixteen bit word driven by sixteen OCDs).
As with other types of DRAMs, a typical DDR SDRAM chip can enter a “power down” state if the system in which it operates is currently not using the DDR SDRAM chip. This power down state can be entered, for example, by the system pulling the clock enable signal (CKE) sent to the DDR SDRAM chip to a low state (the CKE signal is typically in a high state during normal operation). During “power down” the DDR SDRAM chip retains only that information that is currently stored. Accordingly, power consumption of a DDR SDRAM chip is minimized, thus reducing the drain on a battery (e.g., in a mobile device). A power down can legally be entered into only when no read burst is currently active; otherwise, the power down is considered “illegal” and may result in undesirable consequences such as lost data, bus contention, or system contamination, for example.
However, some systems are not able to determine whether a DDR SDRAM is still in a read burst state when the system attempts to send the DDR SDRAM into a power down state. To avoid “hanging up” the system, DDR SDRAMs must screen out the read burst if a power down command is received and the DDR SDRAM illegally enters the power down state during a read burst.
Systems using DDR SDRAM chips are especially sensitive to the DQS line being stuck in the logical high state, since the signal edges of the DQS signals are used to latch the DQ information. If the DQS signal gets “stuck at high,” the DQS OCD continues to drive the line to which it is connected, rather than returning to a non-driving, high impedance state (the “tristate”) during the power down. Under such conditions, if the lines onto which the OCDs drive the DQ data words are also used for writing data into the memory device or are used by other memory devices for reading or writing data, conflicting signals may be present on the lines at once. For example, if another device attempts to drive the DQS line to a logic low state to introduce a new clock transition edge into the system to provide a timing reference for data, the attempt to drive the line may be unsuccessful or timing violations may result due to contention with the DQS signal that is stuck at high.
Disabling a DQS OCD during a signal transition (i.e., the strobe signal transitioning from high to low or from low to high) is also undesirable, since this non-monotonous signal may potentially contaminate the system with several unwanted effects such as ringing, intersymbol interference, etc. Accordingly, it would be desirable to address situations in which a memory device receives a power down signal during a read burst operation such that malfunctions are avoided.